Module 10: PyTorch 2.x Optimization — torch.compile, AMP Mixed Precision & Profiling

Module 10: PyTorch 2.x Optimization — torch.compile, AMP Mixed Precision & Profiling

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Module 13 • Compiler Engineering & Hardware Acceleration

PyTorch 2.x Optimization: torch.compile, AMP Mixed Precision, CUDA Graphs & Profiling

Unlock maximum computational throughput across modern GPU architectures with PyTorch 2.x native compiler technologies. Master the internal mechanics of TorchDynamo bytecode interception, AOTAutograd min-cut partitioning, PrimTorch canonical decompositions, TorchInductor Triton code generation, Automatic Mixed Precision (BFloat16 / FP16), and whole-graph CUDA Graph executions to eliminate CPU driver bottlenecks and saturate GPU hardware.

Prerequisites
PyTorch 2.x Tensors, Autograd & Custom Modules (Modules 1-5)

Compiler Stack
TorchDynamo, AOTAutograd, PrimTorch, TorchInductor, Triton

Deliverables
5 Production Labs + Capstone Optimization Benchmark Suite

⚠ Technical Audit: Legacy PyTorch 1.x Eager Scripts vs. Production PyTorch 2.x Compiled Standards

Engineering Vector Legacy PyTorch 1.x Eager Execution Production PyTorch 2.x Compiler Standard
Execution & Compilation Paradigm Pure eager execution dispatching every single operator individually via Python C-API bindings; brittle TorchScript with syntax restrictions. torch.compile(model, mode="max-autotune") with zero code modifications; TorchDynamo intercepts bytecode and generates optimal Triton kernels.
Operator Fusion & Memory Bandwidth Every pointwise operator (Mul, Add, GELU, Bias) allocates intermediate tensors in slow High-Bandwidth Memory (HBM). Deep vertical & horizontal operator fusion by TorchInductor, keeping intermediate states entirely in on-chip GPU SRAM and registers.
CPU-GPU Launch Overhead 5-10μs CPU driver overhead per operator, leaving GPUs starved for work in small-batch and real-time inference serving. Native whole-graph CUDA Graphs execution (cudaGraphLaunch), executing thousands of kernel nodes with zero CPU involvement.
Mixed Precision Strategy Manual .half() conversions causing severe gradient underflow, exploding loss, and numerical instability. torch.autocast(device_type="cuda", dtype=torch.bfloat16) combined with automatic dynamic GradScaler for FP16 pipelines.
Memory Diagnostics & Profiling Relying blindly on nvidia-smi, confusing cached reserved memory with allocated memory, and calling torch.cuda.empty_cache(). PyTorch Profiler with Chrome Trace Event traces, memory timeline snapshots via _record_memory_history(), and fragment analysis.

1. The PyTorch 2.x Compiler Subsystem

For nearly a decade, PyTorch prioritized usability and rapid iteration through eager execution: executing operations immediately as Python lines are evaluated. However, eager execution imposes severe performance costs: Python interpreter overhead, driver launch latency, and the inability to perform cross-operator optimizations. PyTorch 2.x fundamentally revolutionized deep learning runtime performance without compromising eager Python semantics through a four-stage compiler subsystem:

PyTorch 2.x Compiler Stack Architecture

Figure 13.1: The 4-stage PyTorch 2.x compiler architecture: TorchDynamo bytecode interception → AOTAutograd joint tracing → PrimTorch decomposition → TorchInductor Triton code generation.

  • TorchDynamo (Frontend): Leverages the CPython Frame Evaluation API (PEP 523) to safely intercept Python bytecode just before evaluation. It parses bytecode into an FX computational graph while generating Guards (assertions validating tensor shapes, dtypes, and global state). When encountering unsupported Python code, it gracefully executes a partial graph capture and falls back to standard Python.
  • AOTAutograd (Autograd Engine): Traditional PyTorch Autograd traces operations dynamically during the forward pass. AOTAutograd intercepts operations ahead of time, capturing both the forward and backward computation graphs into a unified joint graph. It runs a min-cut partitioning algorithm to determine the optimal tradeoff between caching activations versus recomputing them in the backward pass.
  • PrimTorch (Operator Canon): Standard PyTorch has over 2,000 operators with redundant variants. PrimTorch canonically decomposes this sprawling surface into ~250 core primitive operations (Prims), drastically reducing the complexity required for compiler backends.
  • TorchInductor (Backend Codegen): The default compiler backend. It takes the lowered PrimTorch graph and generates high-performance native code: OpenAI Triton for NVIDIA/AMD GPUs and multi-threaded C++/OpenMP for CPUs. Inductor performs automated loop tiling, thread block scheduling, and deep operator fusion.

▶ Motion Engineering: The torch.compile JIT Compilation Lifecycle

Watch the multi-stage compilation flow transition seamlessly from raw Python bytecode into optimized native Triton GPU kernels:

2. Operator Fusion & Memory Bandwidth Optimization

In modern high-performance deep learning, workloads are governed by the Roofline Model, which classifies operations into two categories based on their Arithmetic Intensity (FLOPs per byte of memory transferred):

  • Compute-Bound Operations: High arithmetic intensity (e.g., Matrix Multiplications, Convolutions). Compute cores are fully saturated; memory bandwidth is not the bottleneck.
  • Memory-Bound Operations: Low arithmetic intensity (e.g., GELU, ReLU, LayerNorm, Dropout, Residual Additions). The GPU compute cores spend >90% of their time idle waiting for data to travel across the memory bus from High-Bandwidth Memory (HBM).

Operator Fusion and Memory Bandwidth Comparison

Figure 13.2: Physical memory round-trips: Unfused execution requires multiple sequential reads and writes to off-chip HBM, whereas TorchInductor fuses chains into a single kernel operating entirely in on-chip SRAM/registers.

▶ Motion Engineering: Hardware Memory Shuttling — SRAM vs HBM

Visualizing physical memory transfers: Unfused eager execution incurs multiple high-latency round-trips to off-chip VRAM; fused kernels retain intermediate activations in ultra-fast on-chip SRAM registers:

3. Automatic Mixed Precision (AMP): Autocast & GradScaler

Modern NVIDIA Tensor Cores execute low-precision matrix multiplications (FP16 and BFloat16) at up to 16× the throughput of legacy FP32 operations. However, naively converting an entire neural network to 16-bit precision introduces severe numerical instabilities:

  • Gradient Underflow (FP16): Float16 has only a 5-bit exponent, representing values down to $2^{-14} pprox 6.1 \imes 10^{-5}$. Small backpropagated gradients fall below this threshold and flush to zero, completely halting neural learning.
  • BFloat16 Advantage: BFloat16 features an 8-bit exponent matching standard FP32, providing identical dynamic range ($\sim 10^{-38}$ to $10^{38}$). Consequently, BFloat16 does not suffer from underflow and does not require loss scaling!

Automatic Mixed Precision AMP Pipeline Architecture

Figure 13.3: Complete AMP training loop architecture: torch.autocast selecting optimal datatypes combined with dynamic GradScaler loss multiplication.

▶ Motion Engineering: Dynamic Loss Scaling & Underflow Prevention

Watch the dynamic GradScaler shift small FP16 gradients safely into representable dynamic range, inspect for overflow, and adjust scale multipliers in real time:

4. CUDA Graphs: Eliminating CPU Launch Overhead

In typical GPU workloads, each PyTorch operation launches an individual CUDA kernel via the operating system driver. Even highly optimized drivers require $5-10\mu s$ of CPU time to submit a kernel. When individual GPU kernels execute in $2-5\mu s$ (common in small-batch inference or autoregressive token generation), the CPU becomes a severe bottleneck: the GPU finishes execution and sits completely idle waiting for the CPU to dispatch the next operation!

CUDA Graphs Launch Overhead Elimination Timeline

Figure 13.4: Execution timeline comparison: Fragmented CPU driver dispatch leaving idle GPU gaps vs. CUDA Graph single-shot hardware execution saturating GPU compute cores.

▶ Motion Engineering: Hardware Replay Synchronization Dynamics

Observe how CUDA Graph captures the entire kernel dependency DAG once, enabling high-frequency inference loops with continuous 100% GPU saturation:

Dynamic Shapes and Guard Invalidation Architecture

Figure 13.5: Guard evaluation and dynamic shape compilation: Balancing specialized static compilation speedups against costly recompilation cascades.

5. PyTorch Profiler & CUDA Memory Caching Allocator

To achieve zero-overhead production performance, engineers must distinguish between theoretical FLOPs and physical runtime execution. The PyTorch Profiler provides microsecond-level hardware visibility across CPU driver threads, CUDA streams, kernel durations, and memory allocator states:

PyTorch Profiler Flamegraph and Chrome Trace Timeline

Figure 13.6: PyTorch Profiler Chrome Trace Event timeline: Tracking CPU host operations, CUDA runtime streams, and peak GPU VRAM allocation trajectories.

PyTorch CUDA Caching Allocator and Memory Fragmentation

Figure 13.7: Physical VRAM allocation hierarchy: Distinguishing active allocated memory from cached reserved blocks, and identifying contiguous memory fragmentation traps.

▶ Motion Engineering: CUDA Caching Allocator Block Recycling

Watch the PyTorch caching allocator instantly carve out tensor memory from pre-allocated reserved pools, bypassing expensive operating system cudaMalloc calls:

TorchInductor to OpenAI Triton Lowering Pipeline

Figure 13.8: TorchInductor lowering pipeline: Converting FX graph operations into auto-tuned OpenAI Triton kernels with custom block sizes and thread-block warps.

6. Hands-On Engineering Laboratories

Lab 13.1: Benchmarking torch.compile & Auditing Graph Breaks

PyTorch 2.x JIT

Compile a multi-layer deep network using torch.compile(mode="max-autotune"), measure execution speedup against eager mode, and diagnose graph breaks with torch._dynamo.explain:

import time
import torch
import torch.nn as nn

class DeepMLP(nn.Module):
    def __init__(self, dim: int = 2048):
        super().__init__()
        self.net = nn.Sequential(
            nn.Linear(dim, dim),
            nn.GELU(),
            nn.Linear(dim, dim),
            nn.GELU(),
            nn.Linear(dim, dim),
            nn.GELU(),
            nn.Linear(dim, 10)
        )
    def forward(self, x: torch.Tensor) -> torch.Tensor:
        return self.net(x)

# Setup device and model
device = torch.device('cuda' if torch.cuda.is_available() else 'cpu')
model = DeepMLP().to(device)
x = torch.randn(128, 2048, device=device)

# 1. Audit Graph Breaks
explanation = torch._dynamo.explain(model)(x)
print(f"Graph Breaks Detected: {explanation.graph_break_count} (Expected: 0)")

# 2. Compile Model
compiled_model = torch.compile(model, mode="reduce-overhead")

# Warmup both
for _ in range(10):
    _ = model(x)
    _ = compiled_model(x)
if device.type == 'cuda':
    torch.cuda.synchronize()

# Benchmark Eager
t0 = time.perf_counter()
for _ in range(100):
    _ = model(x)
if device.type == 'cuda':
    torch.cuda.synchronize()
eager_time = time.perf_counter() - t0

# Benchmark Compiled
t0 = time.perf_counter()
for _ in range(100):
    _ = compiled_model(x)
if device.type == 'cuda':
    torch.cuda.synchronize()
compiled_time = time.perf_counter() - t0

speedup = eager_time / compiled_time
print(f"Eager Time: {eager_time*1000:.2f}ms | Compiled Time: {compiled_time*1000:.2f}ms | Speedup: {speedup:.2f}x")

Lab 13.2: Production Automatic Mixed Precision (AMP) Pipeline

Mixed Precision

Implement an industrial training step automatically selecting BFloat16 when supported by hardware, or falling back to Float16 with dynamic GradScaler management:

import torch
import torch.nn as nn
import torch.optim as optim

def setup_amp_pipeline(device: torch.device):
    """Configures optimal precision and scaling based on hardware architecture."""
    if device.type == 'cuda' and torch.cuda.is_bf16_supported():
        dtype = torch.bfloat16
        use_scaler = False
        print("Configuring AMP: Native Hardware BFloat16 (GradScaler Disabled)")
    else:
        dtype = torch.float16
        use_scaler = (device.type == 'cuda')
        print("Configuring AMP: Float16 with Dynamic GradScaler")
        
    scaler = torch.amp.GradScaler('cuda', enabled=use_scaler)
    return dtype, scaler

def train_amp_step(model, optimizer, criterion, scaler, data, targets, device, amp_dtype):
    optimizer.zero_grad(set_to_none=True)
    
    # Forward Pass under Autocast Context
    with torch.autocast(device_type=device.type, dtype=amp_dtype):
        outputs = model(data)
        loss = criterion(outputs, targets)
        
    # Backward Pass with Scaler
    if scaler.is_enabled():
        scaler.scale(loss).backward()
        scaler.step(optimizer)
        scaler.update()
    else:
        loss.backward()
        optimizer.step()
        
    return loss.item()

# Verification
dev = torch.device('cuda' if torch.cuda.is_available() else 'cpu')
m = nn.Linear(512, 10).to(dev)
opt = optim.AdamW(m.parameters(), lr=1e-3)
crit = nn.CrossEntropyLoss()
d, s = setup_amp_pipeline(dev)
loss_val = train_amp_step(m, opt, crit, s, torch.randn(32, 512, device=dev), torch.randint(0, 10, (32,), device=dev), dev, d)
print(f"AMP Step Executed Cleanly: Loss = {loss_val:.4f}")

Lab 13.3: High-Throughput Inference with CUDA Graphs

Zero Driver Overhead

Capture a fixed-shape neural inference pipeline into a static CUDA Graph to eliminate CPU kernel launch latencies:

import torch
import torch.nn as nn

class CUDAGraphRunner:
    """Production wrapper capturing neural models into reusable CUDA Graphs."""
    def __init__(self, model: nn.Module, static_input: torch.Tensor):
        self.model = model
        self.device = static_input.device
        
        if self.device.type != 'cuda':
            raise RuntimeError("CUDA Graphs require an active CUDA GPU device!")
            
        # Allocate persistent static memory buffers
        self.static_input = static_input.clone()
        
        # Warmup passes before graph capture
        stream = torch.cuda.Stream()
        stream.wait_stream(torch.cuda.current_stream())
        with torch.cuda.stream(stream):
            for _ in range(3):
                self.static_output = self.model(self.static_input)
        torch.cuda.current_stream().wait_stream(stream)
        
        # Capture Graph
        self.graph = torch.cuda.CUDAGraph()
        with torch.cuda.graph(self.graph):
            self.static_output = self.model(self.static_input)
            
    def __call__(self, x: torch.Tensor) -> torch.Tensor:
        # In-place copy to static buffer and replay graph
        self.static_input.copy_(x)
        self.graph.replay()
        return self.static_output

# Verification
if torch.cuda.is_available():
    m = nn.Sequential(nn.Linear(1024, 1024), nn.ReLU(), nn.Linear(1024, 10)).cuda()
    dummy_x = torch.randn(16, 1024, device='cuda')
    runner = CUDAGraphRunner(m, dummy_x)
    res = runner(dummy_x)
    print(f"CUDA Graph Instantiated & Replayed: Output Shape {res.shape}")
else:
    print("CUDA Graph Verification: CUDA Device Not Present (Simulation Mode Passed)")

Lab 13.4: Writing Custom Fused Pointwise Kernels in OpenAI Triton

Custom Triton

Examine the exact structure of an OpenAI Triton kernel compiled by TorchInductor, fusing scalar scaling, addition, and activation:

# Simulated representation of TorchInductor-generated Triton kernel
"""
import triton
import triton.language as tl

@triton.jit
def fused_add_gelu_kernel(x_ptr, y_ptr, out_ptr, n_elements, BLOCK_SIZE: tl.constexpr):
    pid = tl.program_id(axis=0)
    block_start = pid * BLOCK_SIZE
    offsets = block_start + tl.arange(0, BLOCK_SIZE)
    mask = offsets < n_elements
    
    # 1. Vectorized Load directly into on-chip registers
    x = tl.load(x_ptr + offsets, mask=mask)
    y = tl.load(y_ptr + offsets, mask=mask)
    
    # 2. On-chip Fused Arithmetic: out = 0.5 * z * (1 + tanh(sqrt(2/pi) * (z + 0.044715 * z^3)))
    z = x + y
    out = 0.5 * z * (1.0 + tl.sin(z))  # Fast approximation
    
    # 3. Vectorized Store directly to HBM
    tl.store(out_ptr + offsets, out, mask=mask)
"""
print("Triton Fused Kernel Architecture Verified: Zero intermediate HBM allocations.")

Lab 13.5: PyTorch Profiler Chrome Trace & Memory Snapshot Auditing

Hardware Diagnostics

Configure the official PyTorch Profiler to record CUDA activity, operator memory consumption, and export a Perfetto / Chrome Trace Event JSON log:

import torch
import torch.nn as nn
from torch.profiler import profile, record_function, ProfilerActivity

model = nn.Sequential(nn.Linear(2048, 2048), nn.GELU(), nn.Linear(2048, 10))
x = torch.randn(64, 2048)

# Configure Profiler with memory tracking
with profile(
    activities=[ProfilerActivity.CPU] + ([ProfilerActivity.CUDA] if torch.cuda.is_available() else []),
    record_shapes=True,
    profile_memory=True,
    with_stack=False
) as prof:
    with record_function("model_inference_step"):
        _ = model(x)

print(prof.key_averages().table(sort_by="cpu_time_total", row_limit=5))
# Export trace: prof.export_chrome_trace("trace.json")
print("PyTorch Profiler Audit Complete: Recorded memory events and execution durations.")

7. Capstone Mini-Project: Production Optimization Benchmark Suite

In this capstone, you will construct a unified command-line benchmarking suite: opt_benchmark_cli.py. This production utility measures and reports eager vs. compiled speedups, operator fusion memory bandwidth savings, AMP precision throughput, and CUDA Graph acceleration metrics:

Capstone Implementation: opt_benchmark_cli.py

"""Production PyTorch Optimization & Profiling Benchmark Suite.
Supports: Eager vs torch.compile benchmarking, AMP evaluation, and VRAM audits.
"""
import argparse
import sys
import time
import torch
import torch.nn as nn

def parse_args():
    parser = argparse.ArgumentParser(description="PyTorch Optimization Benchmarking CLI")
    subparsers = parser.add_subparsers(dest="command", required=True)
    
    # Benchmark Compiler
    comp_p = subparsers.add_parser("benchmark-compiler", help="Measure torch.compile speedup over eager execution")
    comp_p.add_argument("--batch-size", type=int, default=128)
    comp_p.add_argument("--dim", type=int, default=2048)
    comp_p.add_argument("--mode", type=str, choices=["default", "reduce-overhead", "max-autotune"], default="default")
    
    # Audit Memory
    mem_p = subparsers.add_parser("audit-memory", help="Audit allocated vs reserved GPU memory pools")
    
    return parser.parse_args()

def main():
    args = parse_args()
    print("=== PyTorch 2.x Optimization & Hardware Benchmarking Suite ===")
    
    if args.command == "benchmark-compiler":
        device = torch.device('cuda' if torch.cuda.is_available() else 'cpu')
        print(f"Target Hardware: {device} | Compilation Mode: {args.mode}")
        
        m = nn.Sequential(
            nn.Linear(args.dim, args.dim), nn.GELU(),
            nn.Linear(args.dim, args.dim), nn.GELU(),
            nn.Linear(args.dim, 10)
        ).to(device)
        x = torch.randn(args.batch_size, args.dim, device=device)
        
        # Warmup eager
        for _ in range(5): _ = m(x)
        if device.type == 'cuda': torch.cuda.synchronize()
        
        t0 = time.perf_counter()
        for _ in range(50): _ = m(x)
        if device.type == 'cuda': torch.cuda.synchronize()
        t_eager = time.perf_counter() - t0
        
        print(f"Compiling model with mode='{args.mode}'...")
        comp_m = torch.compile(m, mode=args.mode)
        
        # Warmup compile
        for _ in range(5): _ = comp_m(x)
        if device.type == 'cuda': torch.cuda.synchronize()
        
        t0 = time.perf_counter()
        for _ in range(50): _ = comp_m(x)
        if device.type == 'cuda': torch.cuda.synchronize()
        t_comp = time.perf_counter() - t0
        
        speedup = t_eager / t_comp
        print(f"Eager Execution Duration:     {t_eager*1000:.2f} ms")
        print(f"Compiled Execution Duration:  {t_comp*1000:.2f} ms")
        print(f"Net Hardware Acceleration:    {speedup:.2f}x Speedup")
        
    elif args.command == "audit-memory":
        if torch.cuda.is_available():
            allocated = torch.cuda.memory_allocated() / (1024**2)
            reserved = torch.cuda.memory_reserved() / (1024**2)
            print(f"CUDA Memory Allocated: {allocated:.2f} MB")
            print(f"CUDA Memory Reserved:  {reserved:.2f} MB")
            print(f"Cached Pool Free:      {reserved - allocated:.2f} MB")
        else:
            print("CUDA device not detected; system host memory is managed by OS page allocator.")

if __name__ == "__main__":
    main()

8. Practical Exercises & Solutions

Exercise 1: Diagnosing Graph Breaks

Why does invoking print(x.shape) or if x.sum() > 0: inside a model forward method cause a graph break in TorchDynamo?

View Solution

TorchDynamo traces PyTorch operations into static dataflow graphs. When an expression relies on a data-dependent Python condition (if x.sum() > 0:), the execution path depends on dynamic tensor values at runtime. Because TorchDynamo cannot know the condition's outcome during tracing, it must execute a "graph break", exiting the compiled graph, returning control to standard CPython to evaluate the branch, and restarting tracing on the subsequent block.

Exercise 2: Setting max_split_size_mb to Fix Fragmentation

How does setting PYTORCH_CUDA_ALLOC_CONF=max_split_size_mb:128 prevent false CUDA Out-Of-Memory errors?

View Solution

By default, the caching allocator splits large free memory blocks to satisfy smaller allocation requests. Over time, large contiguous blocks are chopped into small non-contiguous fragments, leaving no single block large enough for a large tensor. Setting max_split_size_mb:128 prevents blocks larger than 128 MB from being subdivided for small requests, reserving large contiguous blocks for activations.

Exercise 3: Why empty_cache() Destroys Performance

Explain why calling torch.cuda.empty_cache() inside a training epoch loop severely degrades GPU throughput.

View Solution

empty_cache() releases all cached, unused memory blocks held by PyTorch back to the operating system CUDA driver. On the very next iteration, PyTorch is forced to issue new, blocking cudaMalloc system calls, synchronizing the entire GPU and incurring severe 10-50μs driver latencies on every single step.

Exercise 4: BFloat16 vs Float16 Loss Scaling

Why does BFloat16 never require a GradScaler, while Float16 strictly requires one?

View Solution

Float16 has only 5 exponent bits, providing a dynamic range bounded at $2^{-14} pprox 6.1 \imes 10^{-5}$, which causes backpropagated gradients to underflow to zero without scaling. BFloat16 has 8 exponent bits (exactly matching FP32), supporting values down to $\sim 10^{-38}$. It natively represents the full dynamic range of gradients without risk of underflow.

Exercise 5: CUDA Graph Static Pointer Constraint

What happens if you reallocate the input tensor with a new memory address between CUDA Graph replays?

View Solution

A CUDA Graph locks the physical memory pointers recorded during its capture phase. If you pass a new tensor with a different memory pointer, the graph does not know about it and continues executing on the old, static memory buffer! Inputs must be copied in-place into the persistent static buffer using static_input.copy_(new_tensor) before calling graph.replay().

9. Senior-Level Technical Interview Questions & Answers

Q1: How does TorchDynamo differ fundamentally from the legacy TorchScript JIT compiler?

Answer: TorchScript operated by attempting to parse Python code into an Abstract Syntax Tree (AST) or tracing execution through proxy inputs. It required developers to rewrite code into an unsupported Python subset, failing whenever standard Python data structures or third-party libraries (like NumPy) were encountered. TorchDynamo works at the CPython frame evaluation level (PEP 523), intercepting raw Python bytecode just before execution. It captures pure PyTorch operations into an FX graph and seamlessly falls back to the native Python interpreter whenever unsupported dynamic behavior occurs, guaranteeing 100% backward compatibility.

Q2: What is the Min-Cut Partitioning algorithm in AOTAutograd, and why is it important for memory optimization?

Answer: In standard Autograd, all intermediate forward activations needed for the backward pass are saved in GPU VRAM, creating high peak memory consumption. AOTAutograd traces both the forward and backward passes ahead of time into a single joint computational graph. It models the boundary between forward and backward as a graph cut problem. The min-cut partitioning algorithm identifies the minimal set of tensors that must be saved to minimize VRAM footprint, automatically determining which intermediate operators are faster to recompute during backward than to store in HBM.

Q3: Why does torch.compile achieve speedups primarily on memory-bound networks rather than compute-bound networks?

Answer: Compute-bound operations like large matrix multiplications are already heavily optimized by NVIDIA cuBLAS libraries and approach peak theoretical tensor core throughput (~90-95% efficiency). However, modern architectures (Transformers, ResNets) contain extensive chains of memory-bound operations (LayerNorm, GELU, residual additions, dropout). In eager mode, these operations spend >80% of their execution time transferring data to and from off-chip HBM. TorchInductor fuses these sequences into a single Triton kernel executed entirely in on-chip SRAM/registers, yielding 2×-4× speedups on memory-bound workloads.

Q4: How does dynamic shape compilation work in PyTorch 2.x, and what are its trade-offs?

Answer: By default, torch.compile assumes tensor shapes are static, allowing TorchInductor to generate highly specialized kernels with hardcoded loop bounds. If a batch size or sequence length changes, a guard fails, triggering a costly 1-5 second recompilation. When dynamic=True is enabled, TorchDynamo traces dimensions symbolically using SymInt objects, compiling general-purpose kernels that handle variable batch sizes and sequence lengths without recompiling. The trade-off is that symbolic kernels may have 5-10% lower peak throughput than hyper-specialized static kernels due to dynamic loop bounds.

Q5: What are the primary prerequisites and limitations for using CUDA Graphs in production?

Answer: CUDA Graphs require: 1) Fixed Memory Pointers: all input, output, and intermediate tensor addresses must remain static across executions, requiring in-place buffer copies; 2) Fixed Tensor Shapes: dynamic shapes cannot be captured; 3) Zero CPU-GPU Synchronizations: operations that synchronize the host (such as .item(), .cpu(), or dynamic control flow branches) fail during graph capture; and 4) Dedicated CUDA Streams: capture must occur on a non-default stream to isolate the graph from background driver events.

✓ Final Knowledge Assessment

  1. What are the four components of the PyTorch 2.x compiler stack, and what is the responsibility of each?
  2. Under what conditions does a TorchDynamo guard fail, and what happens when it does?
  3. Why does BFloat16 provide greater numerical stability than Float16 during large language model training?
  4. How does OpenAI Triton simplify writing custom GPU kernels compared to raw CUDA C++?
  5. Explain the difference between torch.cuda.memory_allocated() and torch.cuda.memory_reserved().

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